A Verilog HDL library for fixed point-floating point conversion

Generally when people ask for my advice to learn Verilog HDL, I prescribe them this book, this book, this book or this book. But then, learning of a programming language does not complete without practise. So I would suggest that they write a synthesisable, vendor-neutral Verilog code for a simple, fixed point RISC microprocessor and test it by writing a testbench. Later on they can expand then processor to include pipelined processing.

But in recent days, the floating point processors are slowly creeping into the scene, displacing their fixed point counterpart, although the choice between them are extremely application specific.
So I ask the Verilog newbies to try out a floating point RISC processor, additionally. But why do they need to write a testbench separately for the floating point processor, if it is functionally similar to its fixed point counterpart, they wrote at the beginning? I tried searching around and found an extremely useful library (AFFHL).

Frankly the name of this library is not so cool, but its design and its working are impressive. I managed to convert the comprehensive testbench that I wrote for the fixed point processor to a testbench for floating point processor. This hardware library can also convert floating to fixed point, although I have not yet tried it. Simulink has toolbox for floating-to-fixed point conversion. But now a HDL library for that is simply wonderful.

Unfortunately I don't think VHDL has such a library (please correct me if I am wrong). In future you would see such a VHDL library based on AFFHL design in this page, provided the designers permit.