One year ago, when my Debian implementation had some device drivers accidentally messed up, I sat down to write the parallel port and USB device driver myself. Parallel port worked great, but when I was in the file_operation: read part of USB driver, we had a power fluctuation at home crashing my computer. But that operation gave me a chance for understanding the USB architecture.
When USB 3.0 specifications released, I wanted to know how they claim it would be backward compatible. It was all very simple. USB 3.0 has the same bus structure of USB 2.0 with a USB 3.0 superspeed structure added to it in parallel. The baseline topology is the same as USB 2.0 – a tiered star topology. No wonder, it is backward compatible. In the PHY layer, USB 3.0 contains 8 wires instead of four in the previous versions. Out of them, four are the usual USB 2.0 wires, the other four are two superspeed transmitter wires and two superspeed receiver wires. So in physical layer, USB 3.0 is nothing but USB 2.0 tied up with a speedier architecture in the entire PHY layer, with its dedicated spread spectrum clocking (which is known for reducing EMI). This layer also provides a shift register based scrambling. Usually when you design and develop peripherals for USB 3.0, I would advise you turn it off, do your unit testing, and then enable scrambling back (just the same as PCIe development). Otherwise you would have a tough time validating the results.
One of the important features in USB 3.0 is its power management architecture. The power management is done at three loosely coupled levels: localized link power management, USB device power management, USB function power management. You can enable a remote wake feature and wake up any device from remote.
One thing, that is completely in the cloud in the USB chip architecture (proprietary design). I did not find any document in Internet about that. It is a completely mystery how they provide that super speed. USB 3.0 HCI specification does not seem to be completely open yet. From what we know, USB 3.0 looks more like PCI-SIG controller, more specifically express 2 architecture (5 GBPS) packaged differently, although Intel denies it. Both of them use the same encoding scheme, shift register based scrambling, spread spectrum clocking etc. So if you know PCIe 2.0 architecture, then you know more than 50% of USB 3.0. Having said all these, there are a lot of things still hidden. And many of the melodies are still hidden. As Keats says,
Heard melodies are sweet, but those unheard are sweeter.Let’s wait with all ears to listen to the unheard, whenever it gets loud enough.