We are designing all of our future development to multicore designs. We believe this is a key inflection point for the industry.Followed by the diminishing returns from the Instruction-led Parallelism in a uniprocessor, the world of computer architecture decided that multicore processor and chip multiprocessor is the direction of the future.
I knew the importance of multicore processors even before they became famous in the general purpose computing.
Part of my undergraduation research thesis involved implementing digital beamforming in quad-core SHARC processor. Now it is apparent that multicore processors are here to stay and whether you like it or not parallel programming is the future way of computing. Web programs are already running in parallel managed by the web application servers. Embedded systems programming are rapidly moving towards introducing parallelism wherever performance matters. There still are two issues that make parallel programming difficult. One is the availability of debugging tools, especially the rather unique bugs like Heisenbugs. The firms are moving towards developing debuggers to reveal the heisenbugs and ease the programming. Although the multicore developers and compiler designers are coming up with parallel programming debugger extensions to solve this problem, it is clear, present and painful at this stage.Second issue with multicore processor is the lack of simulators for multicore processors. SimpleScalar is certainly a excellent processor simulator. But simulating a Chip MultiProcessor (CMP) with hundreds of core is still an open problem for the computer architecture community. Recently Monchiero et al of Hewlett-Packard Laboratories have come up with an idea to simulate shared-memory CMP of large size, published in the recent SIGARCH transaction.
The best part of this paper is the simplicity of the underlying idea. The idea is to translate the thread-level parallelism of the software to core-level parallelism in the simulated CMP. First step is to use the existing full system simulator to separate instruction streams belonging to different threads. Then the instructions flow of each thread is mapped to different cores of the targeted CMP. And then the final step is simulating the synchronization between the different cores. The simulator explained in this paper can be used to simulate any multithreaded application in a conventional system simulator and extend the evaluation to any homogenous multicore processor. I believe this framework is going to be used in many CMP-simulators in future.
UPDATED ON 02/02/2010: This might be a viable multicore processor simulator.
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Is that simulator available as an open source tool? If so, could you please post the link?
ReplyDeleteIs there any simulator to support multi-core or quad-core??
ReplyDeleteDoes simplescalar support multi-core or quad-core?
@Anonymous
ReplyDeleteStrangely multi-core simulators are rarer species than the multi-core processor itself. Simplescalar LLC cannot support multicore as it is. But you can change it's source code to make it support.
But a better idea is to use IBM Turandot based simulation. There are some tools like Saksham and SimEx. But I have personally never tried them.
If you have more time, you can modify the Simplescalar LLC's code as described here: http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4069171. But do not venture this, if you are running short of time.
hi,
ReplyDeletei am a student doing my undergraduation. can you tell me some open projects regarding processor simulator which i can take up as my final year project. what can i imporve in simple scalar architecture apart from support for multicore can anything else be done. i mean can u give me some ideas so that i can carry forward.
thanks
@Anonymous
ReplyDeleteThere are a lot of things to be improved when it comes to processor simulator. As I said earlier, the processors outpaced the growth of simulators - at least the free ones.
Improving SimpleScalar would make an excellent undergraduation project. A lot can be done other than support for multicore. For instance, dynamic voltage and frequency scaling. It is present in many of the modern processors and will be present in the processors to come.
But without knowing much about you, your interest and your skillset, it would be difficult to offer any advice. The best thing that you can do is to go through the source code of SimpleScalar LLC and then you can list out what can be done and what can be of the best size to be considered an undergraduation thesis and things like that.
hi,
ReplyDeletethanks for the reply. am doing by undergraduation in computer science at sastra in tanjavur,and am interested in processor architecture. i have taken up my project as processor simulator. now i just need a topic to work on. i have two more of my friends as my bacth mates and we are pretty good in c and c++ programming. i am really confused on what to take up as my project so that i can complete it in time and the project comes out good. so if u could help out in exactly wat has to be done with some project titles and how to move on with the project. it would be of great help. once i decide upon the exact title and guidance i am sure that i can carry forward.
my email id is rohitvishnu@gmail.com.
Hi,
ReplyDeleteIs IBM Turandot available for the academic use? I could not find anyway to download it for evaluation?
Hi,
ReplyDeleteAs part of my research work, I'd like to validate my auto-partitioning compiler output in a multi-core simulator environment, rather than running on real hardware. Do you have any suggestion on what tools are avaliable? And is IBM Turando only accessible under commercial license?
Thanks!
@Jing,
ReplyDeleteIBM Turandot is the best I would suggest for your research. But then, it's pricey.
I don't think there is a free version of IBM Turandot available for academic research purpose. But I would suggest you shoot them a mail and ask. They may have some provision, certainly. Also Turandot only supports PowerPC like architecture.
Are you looking for an x86-based processor? If it is x86-based multi-core processor, you can try out Saksham. It is not Turandot, certainly. But it is free.
Ironically, it may be cheaper to run your auto-partitioning compiler in a real hardware.
Thanks Sundar! I'm looking through the Saksham project page now. Actually RISC processors would better fit in my research, rather than x86-based ones. Anyway I'll take a deeper look at Saksham.
ReplyDeleteAnother thing about the SimpleScalar-based PowerPC simulator (parallel multicore edition), I don't you if you are familiar with it or not. I just got to know it from your comments above and gave it a brief tryout. At the first glance, it could run multiple programs (either in EIO trace or in binary format) on multiple cores respectively. But I'm not sure (though particular interested) if the cores can run in a pipeline context (i.e. the first core feeds synchronization signal and data to the second core, and off the second core go, and so on). And how can the cores communicate with each other in that simulator? Is it via shared memory only?
Thanks so much for you comment.
The simulator which is object of this article is named COTSon by HP. This is now freely available on sourceforge: http://sourceforge.net/projects/cotson/
ReplyDeletehi this is biswabandan from iit madras,1st yr masters student working in architecture,specific to microarchitecture and memory hierarchy of multicore.what are the latest simulators available in the market for multicore?is it only simplescalar?
ReplyDeleteI have been visiting various blogs for my term papers writing research. I have found your blog to be quite useful. Keep updating your blog with valuable information… Regards
ReplyDelete@biswabandan panda
ReplyDeleteMemory hierarchy of multicore processor is an interesting research field. You might be using sim-cache, I presume.
Is there any other simulator? Yes, there are. But it depends on the architecture you want to simulate. For an ARM or MIPS like processors, simplescalar is the best choice in my opinion. There is one Simult-ARM for ARM, but I have never tried it.
If you are going to concentrate on general purpose processors like those made by AMD, then you might want to use COTSon. Have you decided on that?
@Term Papers
ReplyDeleteThanks for your appreciation. I will try to keep updating my blog. But there are a lot of things that I am paid to do, which comes into priority on top. So I have not updated my blog for the past three months. I will try to do the due as soon as possible.
hi your blog is very useful for any newcomer in multicore.I am quite interested in multicore architecture. I want to carry out my research in scheduling in multicore..so is it necessary that i have to decide architecture first...I am also in need of some multicore simulator to carry out my research...please answer my query..
ReplyDeleteThanks
@Anonymous
ReplyDeleteIt's necessary for you to at least determine the glimpse of architecture to do research on scheduling. I do not know how you can do a generic scheduling that would work well with all multicore architecture.
thanks for such a comprehensive article
ReplyDelete